Tagged with 20nm, 28nm, cost, FD-SOI, FinFET, foundry, IBS, low-power, markets, mobile, wafers
In a recent study entitled Economic Impact of the Technology Choices at 28nm/20nm, International Business Strategies (IBS) has found that those companies choosing FD-SOI at 28nm and/or 20nm should benefit from substantial savings in cost-per-die (see figure).
For a technology to be utilized in high-volume production, costs must be lower than previous generations of technology. The industry thus faces a critical juncture in the shrink from 28nm to the nodes around 20nm (the precise dimensions of which vary by foundry). Making the wrong technology decisions at ~20nm can cost wafer manufacturers and fabless companies billions of dollars. It is therefore appropriate to analyze the cost factors for the different versions of 28nm as a baseline.
Multiple factors need to be considered with the migration to ~20nm, and the highly visible experience to date in attaining high yielding, volume production on 40nm and 28nm from the industry’s largest players provides visibility into what is likely to happen at 20nm bulk.
IBS has been in the business of modeling and analyzing the impact of technology choices for clients in the semiconductor and related industries for over 20 years. Our robust approach has stood the test of time, enabling us to predict the economic impact of such decisions with a high degree of accuracy.
For the purposes of our analysis, we consider die sizes of both 100mm2 and 200mm2. The flavors we considered are for high-performance (HP) and low-power (LP) chips. The technology options at the 28nm node are high-k/metal-gate (HKMG) bulk CMOS vs. FD-SOI. For the ~20nm node, we add FinFET to the analysis.
Result: FD-SOI die cost less
At the 28nm node, if you only look at the processed wafer cost, the FD-SOI solutions are roughly 7% higher. However, yield issues and the net die/wafer at 28nm have a major impact on the bottom line. When defect densities and parametric yields are factored in, the FD-SOI solution results in a lower per-die cost: from 8% lower for the smaller, low-power chips, to 18% for large, high-performance chips.
At 20nm, however, the FD-SOI processed wafer cost is less than both bulk CMOS and FinFET processed wafers. The FD-SOI processed wafer cost advantage is then massively increased when yields are factored in.
Once ~20nm bulk FinFETs have matured in Q1/2016, FD-SOI will still offer comparative per-die savings of 50-60%.
Related FD-SOI advantages
Power/performance characteristics of FD-SOI will be 30% to 40% superior to bulk HKMG CMOS at 20nm. Analog porting of FD-SOI will be easier than with the other options because of the superior sub-threshold characteristics.
Today, FD-SOI is the only technology that can operate safely in the 0.6V to 0.7V range at 28nm. While there is some reduction in performance, operating power is reduced, giving a very compelling performance-power advantage against other technologies.
Although the real competition is likely to be between FinFETs and FD-SOI at 20nm, FinFETs are a new technology (from a high-volume production perspective), with significant cost penalties even in Q1/2016.
Bulk HKMG CMOS will have low parametric yields at 20nm. A major source of yield loss for bulk CMOS is that of random dopant fluctuations from transistor implants. These implants are not required for FD-SOI. ~20nm FinFET structures will be high-cost to manufacture, and parametric yields will be low.
The time to reach defect density-related yields with allowance impact of parametric yields is estimated to be 12 to 18 months for FD-SOI versus 24 to 36 months for FinFETs.
So compared to bulk CMOS or FinFET, the FD-SOI option cuts ramp time by as much as half.
The faster ramp-up of wafer volumes combined with more predictable yield ramp-up provides additional cost benefits in using FD-SOI over other options at 20nm.
There is ongoing work to assess the further scalability of FD-SOI beyond 20nm to ~14nm and the initial results from IBM and Leti look promising.
Notes on starting parameters
For the purposes of this analysis, the processed wafer costs are derived from experience with leading foundries, for their costs in Q1/13 with eight metal layers (8LM). (Selling prices of processed wafers will of course be higher and will include the gross profit margins of the foundry vendors.) The processed wafer costs include $500 for the ultra-thin SOI wafer used in the FD-SOI process, and $129 for the bulk wafer used in bulk CMOS and bulk FinFET technologies. (While there is the expectation that the SOI wafer prices will be reduced in the future, this is not built into our analyses.)
We assume a high-volume production with utilization rates of about 95%. The bulk version assumes three threshhold voltages (Vt) in the core of the chip, and takes into account support for SRAMS and interfaces. The FD SOI cost is based on 1Vt level for the core and use of body biasing. Body biasing can give two additional Vt levels in the core, which is equivalent to bulk CMOS design options.
Wafer and die costs vary at different stages of maturity. For FinFETs, for example, the cost takes into account the relatively long time for metrology checking in the process and also the manufacturing complexity related to the FinFET structures.