Adele HARS on August 31, 2012
Tagged with 14nm, 20nm, Cadence, FinFET, Freescale, GSS, IBM, IMEC, Intel, Leti, NXP, SOI, Soitec, ST, Synopsys, U. Glasgow
Are FinFETs better on SOI? In a series of papers, high-profile blogs and subsequent media coverage, Gold Standard Simulations (aka GSS) has indicated that, yes, FinFETs should indeed be better on SOI.
To those of us not deeply involved in the research world, much of this may seem to come out of nowhere. But there’s a lot of history here, and in this blog we’ll take a look at what it’s all about, and connect a few dots.
The GSS IEDM ’11 Paper
GSS is a recent spin-off of Scotland’s University of Glasgow – but there’s nothing new to the research community about these folks. The core GSS-U.Glasgow team has been presenting important papers on device modeling at IEDM (which is one of the most prestigious of our industry’s conferences) and elsewhere for many years.
At the risk of stating the obvious, accurate simulations are incredibly important. Technologists need to be able to predict what results they can expect from different possible transistor design options before selecting the most promising ones. Then they also need to provide reliable models to designers who will use them before committing chips to silicon. One of the biggest challenges is predicting variability, which as we all know is getting worse as transistors scale to ever-smaller dimensions.
At IEDM ’11 last December, GSS-U.Glasgow presented Statistical variability and reliability in nanoscale FinFETs. This covered “A comprehensive full-scale 3D simulation study of statistical variability and reliability in emerging, scaled FinFETs on SOI substrate with gate-lengths of 20nm, 14nm and 10nm and low channel doping…”. Essentially they concluded that scaling FinFETs on SOI should be no problem – and in fact the statistical variability of a 10nm FinFET on SOI would be about the same as the industry’s currently seeing in 45nm bulk CMOS.
That paper was based on work that the GSS-U.Glasgow team had done on two major European projects: the EU ENIAC MODERN project, and the EU FP7 TRAMS project. It’s perhaps worth looking a little more closely at what those projects are about – and who’s involved:
- A key objective of the MODERN (for Modeling and Design of Reliable, process variation-aware Nanoelectronic devices, circuits and systems) is to develop “effective methods for evaluating the impact of process variations on manufacturability, design reliability and circuit performance”. Other partners in the project include ST, Leti, NXP, Infineon, Numonyx (now Micron) and Synopsys.
- The objective of the TRAMS (for ‘Tera-scale Reliable Adaptive Memory Systems’) project is “to investigate in depth potential new design alternatives and paradigms, which will be able to provide reliable memory systems out of highly unreliable nanodevices at a reasonable cost and design effort”. Other partners in the project include Intel, imec, and UPC/BarcelonaTech.
A few months later, when Chipworks published pictures of the (bulk silicon) Intel 22nm FinFETs, the folks at GSS started a series of blogs that caught the attention of major tech pubs such as EE Times, Electronics Weekly and EDN. For reference, here are the blogs and basically what they concluded:
- Simulation analysis of the Intel 22nm FinFET (9 May ’12) – using their TCAD simulator GARAND, GSS found the essentially triangular (rather than a rectangular) shape “contributed to worsening of short-channel effects (SCE)”
- Process-induced variability in the Intel FinFETs (6 June ’12) – continued the analysis by looking at process variability, and concluded that there was “a reduction in the on-current by 12-15% compared to rectangular-gate bulk FinFETs”
- FD SOI FinFETS can offer better performance than bulk FinFETs (27 July ’12) asked:
“Assuming that you can make ideal rectangular bulk and SOI FinFETs, which one will have better performance?” The answer: SOI.
Specifically, the July 27th blog indicated that if FinFETs are rectangular in shape, drive current would be 12-15% better. Would that be easier to do on an SOI wafer? Soitec has argued that their “fin-first” SOI-based approach to FinFET manufacturing will save both time & money while getting better results (see Soitec’s Wafer Roadmap for Fully Depleted Planar and 3D/FinFET in Semiconductor Manufacturing & Design).
The GSS blog also reminded readers that the company’s CEO and founder, Asen Asenov (an extremely heavy hitter who’s published over 550 papers), has hinted that “…SOI FinFETs with an almost ideal rectangular shape may be a better solution for future FinFET scaling”. GSS has noted previously that “FinFETs built on an SOI substrate could have significant advantages terms of simpler processing, better process control and reduced statistical variability”.
Fin shape aside, GSS said that by virtue of the layer of insulation, SOI would give another 5% boost to FinFET drive current. But perhaps more importantly, that layer of insulation in SOI-based FinFETs would deliver on average 2.5 times less leakage – which would translate into a doubling of battery-life for your cell phone.
IBM has now entered into an agreement with GSS et al on a project called StatDES, for Statistical Design and Verification of Analogue Systems – see last month’s IBM blog by IBM Research Scientist Dr. Sani Nassif, entitled “Fins on transistors change processor power and performance”.
Dr. Nassif writes, “IBM, University of Glasgow and the Scottish Funding Council are collaborating on a project to simulate 3D microprocessor transistors at a mere 14 nanometer scale (the virus that causes the common cold is more than twice as large at 32 nanometers). Using a silicon-on-insulator (SOI) substrate, the FinFET (fin field-effect transistor) project, called StatDES, promises to keep improving microprocessor performance and energy conservation.”
The steering group also includes folks from ST, Freescale, Wolfson and Cadence, so one would guess we’ll be hearing more from this project – and others like it, to be sure – in the future, wouldn’t you think?