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ST White Paper Excerpts: Planar Fully-Depleted Silicon Technology to Design Competitive SOCs at 28nm and Beyond

Posted by , and (Soitec) on April 24, 2012
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STMicroelectronics recently issued a major white paper detailing the choice of FD-SOI for consumer SOCs at 28nm and beyond. This article excerpts some of the highlights.

From “Planar Fully-Depleted Silicon Technology to Design Competitive SOC at 28nm and Beyond” (White paper by STMicroelectronics and Soitec):

“ FD-SOI Executive Summary

Planar FD is a promising technology for modern mobile and consumer multimedia chips. It combines high performance and low power consumption, complemented by an excellent responsiveness to power management design techniques. The fabrication process is comparatively simple and is a low-risk evolution from conventional planar bulk CMOS – and there is little disruption at the design level, too.

At 28nm, we find that planar FD more than matches the peak performance of “G”-type technology, at the cost and complexity of a low-power type technology, with better power efficiency across use cases than any of the conventional bulk CMOS flavors.

Looking further, for 20nm and 14nm, we believe planar FD will be extremely competitive with respect to alternative approaches in terms of performance and power, while being both simpler and more suited to low-power design techniques. In short, a better choice for the type of SOC we offer.

Planar fully depleted silicon technology will be ready as early as 2012 to compete in the forthcoming superphones era and in many other consumer segments. ”

Having identified that conventional planar bulk CMOS would not meet all the requirements of mobile and consumer multimedia System-on-Chip (SOC) ICs in the coming years, STMicroelectronics assessed alternative options. It is possible to propose a 28nm planar FD solution available as a second generation shortly after readiness of traditional 28nm on bulk silicon, with better time-to-market than waiting for availability of the 20nm node. It is also an excellent learning step to prepare a 20nm planar FD process. Our evaluations show that 20nm planar FD has also a very competitive potential performance-wise vs. FinFET for System-on-Chip applications.

ST Technology Overview

Figure 1: ST’s planar FD device structure features (notional perspective, notional cross-section, TEM cross-section):

  • Immunity to Short Channel Effects and variability (no channel doping, so no Random Doping Fluctuations / RDF)

  • For the 28nm node, the selected BOX thickness is 25nm.

  • Ultra-thin BOX advantages include:

    - further improved electrostatic control and relaxed thinness requirement of the top silicon,

    - enables back-biasing through the BOX,

    - enables the implantation, during the fabrication process, of heavily doped “ground planes” or “back-planes” under the BOX, for improved electrostatics and/or VT adjustment and/or best-efficiency of back-bias,

    - brings the ability, during the fabrication process, to locally remove the top silicon and BOX to reach the base bulk silicon and co-integrate a few (non geometry-critical) devices on Bulk with devices on SOI – with a small step height between an SOI zone and a Bulk zone, compatible with lithography tools.

  • BOX offers total dielectric isolation of the very thin active layer and naturally ultra-shallow junctions, leading to lower source/drain capacitance, lower leakage and latch-up immunity.

Planar FD technology allows several methods for setting the threshold voltage VT, including engineering the gate stack work function, trimming the gate length and other process engineering techniques. Thanks to this, STMicroelectronics’ 28FDSOI technology is capable of offering 3 VTs (HVT, RVT, LVT), as in traditional bulk CMOS technologies.

Circuit-Level Benchmarking

To assess how the improved planar FD-SOI transistor characteristics translate at the circuit level, STMicroelectronics has benchmarked a number of representative IP blocks, including an ARM Cortex-A9 CPU core. To that aim, we have extracted logic critical paths with associated RC parasitics from placed-and-routed designs and have re-characterized them by swapping 28nm traditional bulk CMOS transistor SPICE models with 28nm planar FD SPICE models.

With test chips in our 28nm planar FD technology becoming available, we are demonstrating that

the models predict well the silicon behavior. We are therefore confident that the benchmarks presented below are reliable and will be matched by SOC implementations.

The benchmarks compare the merits at the 28nm node of ST’s planar FD technology (“28FD”) with a state-of-the-art Low-Power technology (“28LP”) and a more performance-oriented, state-of-art General Purpose technology (“28G”). They are all based on evaluation of an ARM Cortex-A9 core. The analysis focuses on the higher end of the range of operating frequencies found in a SOC, since modern mobile and consumer multimedia demand high performance from their master CPU (for example, a Cortex-A9 or the forthcoming A15).

Performance at nominal Vdd : best speed/leakage trade-off: 28FD consistently outperforms both 28LP and 28G (Figure 2).

Figure 2: Best operating frequency for any class of leakage (TT process, 85C)


Excellent
speed/leakage ratio maintained at reduced Vdd : reducing Vdd is a very good way to save dynamic power. It is therefore realistic to envisage building 28FD chips that match 28G or 28LP performance at a fraction of the power consumption.

Leading-edge performance across the full Vdd range: 28FD exhibits outstanding performance at all practical Vdd values. In particular, when maximum circuit speed is sought, only the low- and ultra-low-VT flavors of 28G compare with 28FD LVT; however they are much leakier and more limited in terms of, e.g., Vdd overdrive they can withstand without reliability concerns.

Best Power Efficiency Across Use Cases: the 28FD technology is power-efficient across the full Vdd and target frequency range (Figure 3). Contrary to G-type technology, with 28FD a given logic circuit that is power-efficient with Vdd set to reach a certain operating frequency (say, 2GHz range) remains efficient with Vdd set for a different target frequency range (e.g., sub-1.5GHz).

Figure 3: Power efficiency across all use cases (TT process, WC temp)


Focus on SRAM: 
The bitcells proposed in 28FD technology have very competitive cell current (Icell) vs. standby current ratio, which is representative of the performance/leakage power trade-off for SRAM arrays (Figure 4). This is true for all bit cells flavors: high-density and low-leakage oriented, or high-speed oriented. The footprint of the 4 bitcells proposed in 28FD is the same as that of the 4 bitcells proposed in 28LP.

Figure 4: SRAM memory bit cells performance/leakage. The power supply of 28FD SRAM arrays can be lowered by 100mV from nominal and still match the performance of 28LP SRAM arrays operated at nominal Vdd, while offering a 2x to 5x reduction in leakage power.

Commonalities with 28nm LP Bulk

STMicroelectronics’ strategy when developing the 28nm planar FD technology has been to reuse as much as possible the 28nm low-power bulk CMOS process.

Overall, the Back-End is 100% identical to the traditional 28nm bulk low-power CMOS process, and the Front-End of Line (FEOL) is 80% common with that same process.

The planar FD process saves about 10% of the steps required to fabricate the chips on the wafers. This approximately offsets the cost overhead of the starting wafers. As a result, the 28nm planar FD technology matches the cost of a conventional low-power technology while delivering extremely competitive performance.

Design Considerations

Designing on planar FD requires specific extraction deck and SPICE models. Apart from that, the design flows, methodologies and tools do not need any adaptation that would be specific to planar FD (Figure 5).

Figure 5: ST’s SOC implementation flow outline


SPICE
Models: SPICE compact models have been developed for accurately representing planar FD transistors. The model we use is now integrated in all major commercially available simulators, such as Mentor’s ELDO, Synopsys’ HSPICE and XA or Cadence’ SPECTRE. A model card has been extracted for all transistors and other devices available in our 28nm planar FD technology.

Flow and Design Platform: With adequate SPICE models integrated in the PDK, the design flow is identical to that used with conventional 28nm Bulk CMOS technology. We have developed a full design platform for SOC, re-using work done for 28nm Bulk. It consists of standard cell libraries (multi-channel and multi-VT) with power management elements (power switches, level shifters etc.), embedded memories, analog foundation IP (such as PLLs and the likes) and specialty IP (Antifuse etc.).

A design platform developed for bulk CMOS technology can be ported to planar FD by re-characterization using planar FD SPICE models, which we have done for a variety of back-biasing conditions. Only a limited number of critical IPs need to be tuned or redesigned: Analog IP, IOs, Fuse.

At the SOC level, migrating an existing design from bulk to planar FD represents an effort comparable to half-node migration. It brings very worthwhile benefits at reasonable efforts.

All techniques used in low-power designs are applicable to planar FD. Those that can be enhanced with planar FD include: multi-VT, power switches, reverse and forward body bias, and voltage scaling.

Back-biasing consists of applying a voltage just under the BOX of target transistors. Doing so changes the electrostatic control of the transistors and shifts their threshold voltage VT, to either get more drive current (hence higher performance) at the expense of increased leakage current (forward back-bias, FBB) or cut leakage current at the expense of reduced performance. While back-bias in planar FD is somewhat similar to body-bias that can be implemented in bulk CMOS technology, it offers a number of key advantages in terms of level and efficiency of the bias that can be applied.  Back-biasing can be utilized in a dynamic way, on a block-by-block basis. It can be used to boost performance during the limited periods of time when maximum peak performance is required from that block. It can also be used to cut leakage during the periods of time when limited performance is not an issue. In other words, back-bias offers a new and efficient knob on the speed/power trade-off.

Perspectives

28nm: We expect to sign-off designs breaking the 2GHz barrier under worst-case conditions, in a power-efficient and cost-efficient way. For lower performance targets, there is also the opportunity to design ultra-low-power chips that can fulfill their functional specifications using a very low Vdd, for example in the 0.6-0.8V range. The Process Design Kit (PDK) is available, targeting the technology to be open for risk production by mid-2012.

20nm: We intend to scale our planar FD technology to 20nm, introducing a number of improvements to continue pushing the performance and retain a low power consumption. The objective is to bring up a solution that will improve on what mobile-optimized planar bulk CMOS will achieve, and will be extremely competitive vs. potential FinFET-based approaches for SOC – while keeping a simple and cost-efficient approach. The design rules will be compatible with 20nm bulk CMOS. This technology will bridge the gap to 14nm and provide an interesting alternative to the cost and complexity of introducing Extreme-UV and FinFET structures. Evaluation SPICE models are available, and full PDK is scheduled by end of 2012, with risk production for 13Q3.

14nm: Based on the assessments we have performed, we are confident that the planar FD technology is shrinkable to 14nm. Silicon and buried oxide thickness will need to be reduced to within limits that wafer manufacturers and CMOS process technology can handle.