ASN #18 - News & Viewpoints - SOI In Action

FDSOI Processes are Cost Competitive with Bulk

Posted by (IC Knowledge LLC) on October 19, 2011
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A new study compares processes for the 20/22nm generation at a typical foundry.

Silicon On Insulator (SOI) has been in use for state-of-the-art integrated circuit (IC) manufacturing since IBM first championed the technology in the mid-nineties. SOI offers process technologists the option of reducing power or improving performance for a given process node.

As process technology has continued to advance it has become practical to manufacture SOI wafers with silicon layers that are thin enough for  Fully Depleted SOI (FDSOI).  Also referred to as Extremely Thin SOI (ETSOI), FDSOI processes offer process technologists the opportunity to significantly simplify the process of manufacturing an IC.

IC Knowledge, the world leader in IC cost and economics was retained by Soitec, the world leader in SOI wafer manufacturing, to compare the cost of a FDSOI process versus a Bulk process for 22nm/20nm foundry logic processes.

Threshold voltages

One of the challenges of state-of-the-art foundry processes is providing the multiple threshold voltages required for power management and performance. At a minimum an additional threshold voltage requires two threshold adjust masks and associated implants.

As process geometries have shrunk additional threshold voltages may also require tailoring of source/drain (S/D) extension and halo implants and even S/D contact implants (both extension/halo and contacts each require multiple implants to fabricate).

The result is a single threshold voltage can require up to five masks and fifteen implants.

FDSOI on the other hand can provide multiple threshold voltages by alternative means (including the option to shift the threshold voltage by actively controlling the biasing of the back gate),  eliminating the need for threshold adjust masks and implants entirely.

Process simplification

An FDSOI foundry process with eight metal levels and three threshold voltages can be fabricated with up to fifteen less masking steps and forty-eight fewer implants than a similar bulk process. The resulting process simplification was found to more than offset the higher cost of the starting SOI substrate and result in a cost competitive process versus bulk with better performance.

As processes scale down to 22nm/20nm and beyond standard bulk process transistors can no longer be scaled down without exhibiting unacceptable leakage properties. Techniques such as FDSOI offer better control of the transistor channel and far lower leakage making them a viable technical solution to leakage problems. As has been shown in this study FDSOI also offers an economically viable solution.

In conclusion FDSOI processes offer sufficient process simplification to offset the additional cost of the starting SOI substrate and be cost competitive with bulk processes.

Note: the full FD-SOI cost report is available as a free download from IC Knowledge.