Adele HARS on March 11, 2011
Tagged with AMD, IBM, ISSCC, Leti, PD-SOI, ST
The International Solid-State Circuits Conference – better known as ISSCC – is of course where the big guns show us their big advances at the chip level. At the most recent conference, held a few weeks ago in San Francisco, advances that leveraged SOI were once again at the forefront.
As always, performance gains generate plenty of buzz. But the SOI papers were also notable for work reducing power consumption, extending scalability and overcoming threshold voltage variation.
IBM presented the world’s highest frequency microprocessor to date, clocking in at 5.2 GHz. On 45nm SOI, it’s the first commercial processor ever to break through the 5GHz speed barrier, and is the centerpiece of Big Blue’s new zEnterprise 196 system.
In another paper, IBM presented the first embedded high-k/metal-gate (HK/MG) SRAM on 32nm SOI enabling operation at down to 0.7V.
AMD presented its Bulldozer 2-core modules, which are on 32nm SOI with HK/MG. Clocking in at 3.5GHz, we’ll see them beginning in desktop and server Fusion chips this year.
In a quieter but clearly significant paper, ST and Leti compared 65nm low power (LP) partially depleted (PD) SOI with standard 65nm LP CMOS bulk. They found that PD-SOI, when combined with a low resistivity produced with forward body bias of the power switch, can reduce leakage current by 52.4% vs. bulk and increase the frequency by 20% at 1.2V, while decreasing power by 30% at 360MHz.
For summaries of additional SOI-based papers at ISSCC and other recent conferences, see ASN’s PaperLinks.