ASN #17 - In & Around Our Industry - MEMS - News & Viewpoints

SOI for MEMS: A Promising Material

Posted by (Yole Développement) on March 25, 2011
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A new Yole report highlights growth of SOI MEM S.

Although MEMS technologies are not driven by CD shrinking as ICs, that does not mean MEMS do not undergo strong technological evolutions. The ever-growing MEMS markets, today mostly driven by consumer applications, now have to be performance-driven, cost-driven and size driven.

SOI wafers are a promising substrate for MEMS manufacturing. We estimate the SOI market for MEMS devices will be close to $100M by 2015 (see Figure 1).   That represents a CAGR (2011-2015) of 15.6% for SOI, compared to 8.1% for bulk silicon-based solutions.

 

Figure 1: Substrate Market for MEMS

One main reason for using SOI is to have more design freedom. Tronics, for example is using SOI with High Aspect Ratio Micromachining technology. This technology was developed to manufacture high performance custom inertial sensors (accelerometers and gyroscopes).

Other reasons cited for choosing an SOI-based solution for MEMS include the need for the smallest possible package, very tight control and precision of the structure, ability to withstand high pressure and temperature, long product lifetime, smallest possible die size and reduced cost.

Additional features in SOI wafers can further simplify MEMS design and manufacturing. For example, “cavity-SOI”, in which the SOI wafer has pre-etched cavities, enables the MEMS manufacturers to focus on their core competencies in reducing development time, which in turn can even lower production costs. Some MEMS manufacturers have found that pre-etched SOI cavities combined with dry etching simplifies the release of the devices.

MEMS manufacturers using cavity-SOI include VTI Technologies, Invensense and other players in the seismic accelerometer (Tronics)  and pressure sensor markets.

Figure 2 shows a roadmap for SOI wafers for MEMS. From “traditional” SOI, we are now using SOI with pre-etched cavities. Further developments will allow the realization of SOI wafers with trench isolation, cavities and Through Silicon Vias (TSV).

Suppliers of other substrate solutions are following similar added-value paths. Glass, for example, can be used as a thin wafer carrier for wafer level capping and/or packaging with Through Glass Vias interconnect.

Overall, we believe substrates will  provide additional functionalities in the future, enabling more integrated MEMS devices.

 

Figure 2: Roadmap for SOI Wafers for MEMS

The information in this article is taken from the Yole Report “Trends in MEMS Manufacturing & Packaging”. Contact Yole Development for more information about  reports and services.