Tagged with FD-SOI, SOI Consortium
The third installment in the SOI Consortium’s ongoing FD SOI Workshop series, the Tokyo event was a major success.
The University of Tokyo recently hosted a hugely successful one-day workshop on the FD SOI ecosystem’s readiness. The event took place on Saturday, the 25th of September 2010, at the University of Tokyo’s Komaba Research Campus, following the SSDM Conference. (SSDM is one of the most important international conferences held in Japan.)
Turnout was excellent, with over 120 participants representing academia and most of the major IDM, foundry and fabless players in attendance.
Following the success of the two earlier workshops on Planar Fully-Depleted SOI Technology, the Tokyo edition was organized by Tokyo University, the SOI Consortium and Soitec.
After opening remarks by Toshiro Hiramoto of Tokyo University, compelling presentations from high-profile experts in the industry covered several key aspects of the technology.
All presentations from the Tokyo FD SOI Workshop (as well as all the other workshops in the FD SOI series) are now freely available for downloading from the SOI Consortium website.
Topics covered included:
- Transistor technology and integration approaches (talks by Bruce Doris of IBM; Nobuyuki Sugii of Renesas; and Carlo Reita of Leti)
- Application requirements and suitability of FD SOI (talks by Frédéric Bœuf of STMicroelectronics; and Koichiro Ishibashi of Renesas)
- SPICE model readiness (talks by Tsu-Jae King Liu of UC Berkeley and Shuhei Amakawa of Hiroshima University)
- Supporting the ecosystem (talks by Carlo Reita of Leti; Horacio Mendez of the SOI Consortium; and Olivier Bonnin of Soitec)
- FD benchmarking flows and results (talks by Frédéric Bœuf of STMicroelectronics and Mustafa Badaroglu of IMEC)
- Design flow (talk by Jean-Luc Pelloie of ARM)
Compelling Results Presented
On the technology side, the speakers emphasized that FD SOI solves variability and scalability issues in a cost-effective manner, with high-quality starting wafers available now.
In terms of Power / Performance / Area benchmarking, ST had compelling results on projected FD performance and power advantage at 28nm and 20nm, both for logic and for SRAM. Furthermore, additional strain or design techniques that have not yet been taken into account could further widen the gap.
UC Berkeley presented work on the VDDmin and yield of 20nm 6T SRAM arrays. They predict 30% larger bit cells on bulk to reach the same 6-sigma yield as on FD SOI – and this for a Vmin that is 200mV worse than what FD SOI can achieve.
Jean-Luc Pelloie of ARM made it clear that there is basically no specificity to design on FD SOI: same tools, same flows, and easy porting of foundation IP.
Kazunari Ishimaru of Toshiba concluded with an action item: it is time for the IC industry to start a pilot product.