ASN #15 - Design & Manufacturing - In & Around Our Industry

The Moment Is Now

Posted by (Hitachi) on July 26, 2010
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There’s no need to wait – Hitachi’s SOTB solution also benefits today’s mainstream low-power nodes.

Hitachi’s Hybrid Silicon-On-Thin-Box (SOTB)-Bulk technology offers many benefits for low-power system-on-chips (SOCs) at 45nm –  and even at 65nm. There is no reason to wait for 22nm to start taking advantage of them.

The four most significant reasons to change to this solution now rather than later are that hybrid SOTB:

1. cuts power and leakage in half

2. gets threshold voltage (Vt) and variability under control

3. is fully compatible with current bulk design is easy to manufacture.

4. is easy to manufacture.

Power down: 50%

Over the last 15 years, supply voltage (Vdd) has steadily been reduced from 3V down to 1V. But at 1V, the industry has hit a wall due to Vt variability.

Thanks to its low-dose channel structure and excellent short-channel-effect (SCE) immunity, SOTB has very small Vt variability. It also reduces inter-die Vt variation through the use of back-gate (BG) bias control.

This means that at constant leakage, Vdd can be reduced by 0.3V.  Simulations indicate that SOTB can go further — drastically improving the minimum operating voltage of an SRAM to 0.51V.

For low-power SOCs, the multiple Vt- and back-bias control maximizes both performance and power.

SOTB/Bulk Hybrid Integration: FD-SOI and bulk can co-exist side-by-side (source: T. Ishigaki et al., SSDM., p. 886, 2007 © Hitachi, Ltd. 2009)

Bulk compatible design & manufacturing

SOTB enables implementation of a hybrid bulk-SOI solution. By etching back the thin top silicon and removing the thin BOX layer, bulk transistors can be implemented alongside fully-depleted SOI transistors. This makes SOTB completely compatible with current bulk CMOS design.

This is appealing for a number of applications, including:

  • SRAMs (smaller area, lower VDDmin, better yield),
  • SRAMs plus logic,
  • and fully refurbished designs leveraging SOTB with back-gate bias control.

In terms of manufacturing, the process steps are very straight-forward, including:

  • a single, mid-gap metal gate, suitable for both N- and P-MOS
  • some selective epitaxial growth (SEG).

Designers and manufacturers can leverage a variety of options for fast implementation of SOTB. There’s no need to wait for the 22nm node – the moment to change is now.