IEDM (International Electron Devices Meeting)

Posted on July 26, 2010
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7-9 December 2009, Baltimore, MD, USA
The IEEE’s International Electron Devices Meeting (IEDM) is the world’s showcase for the most important applied research breakthroughs in transistors and electronics technology.
Here is a comprehensive listing of the papers of interest to the SOI and advanced substrates community.

Dual metallic source and drain integration on planar Single and Double Gate SOI CMOS down to 20nm: Performance and scalability assessment
Hutin, L., et al. (Leti)
The paper reports on the fabrication, electrical characterization and TCAD simulation of planar Single and Double Gate n-and p-MOSFETs with metallic Dopant Segregated Source and Drain (DSS) on SOI, with gate lengths down to 20 nm. pFET devices with promising electrical behavior suitable for high performance applications are reported on. Excellent SCE control is also reported down to 30 nm through the use of Double Gate transistors.

Extremely thin SOI (ETSOI) CMOS with record low variability for low power system-on-chip applications
Cheng, K., et al.(IBM)
The authors present a new ETSOI CMOS integration scheme. A single mask level is required to form raised source/drain (RSD) and extensions for both NFET and PFET. Respectable device performance along with low GIDL makes these devices attractive for low power applications. Record low VT variability is achieved. The new process flow is also capable of supporting devices with multiple gate dielectric thicknesses as well as analog devices, which are demonstrated with excellent transconductance and matching characteristics.

Hybrid FDSOI/bulk High-k/metal gate platform for low power (LP) multimedia technology
Fenouillet-Beranger, C., et al. (CEA-Leti)
The authors present FD-SOI with High-K and Single Metal gate as a possible candidate for LP multimedia technology. The interest of Ultra-Thin Buried Oxide substrates (UTBOX) is reported in term of Multiple Vt achievement and matching improvement. Thanks to a hybrid FDSOI/bulk co-integration with UTBOX all IP’s required in a SOC are demonstrated for LP applications.

Experimental and physics-based modeling assessment of strain induced mobility enhancement in FinFETs
Serra, N et al. (U. Udine)
This study combines direct measurements of channel strain, electrical mobility measurements and a rigorous modeling approach to provide insight about the strain induced mobility enhancement in FinFETs and guidelines for the device optimization. The model is then used to systematically explore the impact of the fin-width, fin-height and fin-length stress components on n- and p-FinFETs mobility and to identify optimal stress configurations.

Scaling deep trench based eDRAM on SOI to 32nm and Beyond
Wang, G. et al. (IBM)
A high performance embedded DRAM with deep trench capacitor and high performance SOI logic has been deployed in 45nm and 32nm technology nodes. The authors present, for the first time, a 32nm eDRAM technology fully compatible with high performance logic with high-k metal gate access transistor and high-k node dielectric for the deep trench storage capacitor. A clear scaling path is seen for the 22nm technology node.

Experimental assessment of self-heating in SOI FinFETs
Scholten, A.J.; et al. (NXP, TSMC)
In this paper, it is shown that self-heating causes a gigantic effect on the capacitances of MOSFETs/FinFETs. The effect is used to determine the SOI FinFET thermal impedance and to determine the temperature rise during FinFET operation.

Dual channel FinFETs as a single high-k/metal gate solution beyond 22nm node
Smith, C.E., et al. (Sematech)
The authors report on the promise of dual channel materials using FinFETs for high-performance CMOS for sub 22 nm technology node. They demonstrate pFinFETs with all SiGe channel formed by Germanium condensation onto a Silicon-On-Insulator carrier wafer (SiGeOI) followed by cMOS processing. The devices exhibit 3.6X hole mobility enhancement over Silicon (100) while allowing for VTH control with single high-k and metal gate stack. These attributes taken together constitute a simple non-planar cMOS integration sequence with enhanced drive current for future high performance technology nodes.

Challenges and solutions of FinFET integration in an SRAM cell and a logic circuit for 22 nm node and beyond
Kawasaki, H. et al. (Toshiba, IBM)
FinFET integration challenges and solutions are discussed for the 22 nm node and beyond. Fin dimension scaling is presented and the importance of the sidewall image
transfer (SIT) technique is addressed. Diamond-shaped epi growth for the raised source-drain (RSD) is proposed to improve parasitic resistance (Rpara) degraded by 3-D structure with thin Si-body. The issue of Vt-mismatch is discussed for continuous FinFET SRAM cell-size scaling.

Advances in 3D CMOS sequential integration
Batude, P. (CEA/Leti, Minatec)
For the first time 3D sequential CMOS integration turns up to be an actual competitor for sub 22nm technology nodes. Thanks to the original use of molecular bonding, high quality top Si active layers are obtained. Thermally robust bottom salicide goes through the whole top FET processing without any significant sheet resistance degradation. The low temperature integration of raised source and drain for top layers is demonstrated. The electrostatic coupling between stacked FETs is demonstrated thanks to an ultra thin inter layer dielectric thickness of 60nm. It leads to a threshold voltage dynamic shift of 130mV enabling SRAM stabilization.

Technologies to further reduce soft error susceptibility in SOI
Oldiges, P. et al. (IBM)
Methods for soft error rate reduction in silicon on insulator devices and circuits are explored and evaluated via simulations that have been validated against hardware measurements.

High Performance and Highly Uniform Gate-All-Around Silicon Nanowire MOSFETs with Wire Size Dependent Scaling
Bangsaruntip, S., et al. (IBM)
The authors demonstrate undoped-body gate-all-around (GAA) Si nanowire (NW) MOSFETs with excellent electrostatic scaling. These NW devices, with TaN/Hf-based gate stack, have high drive-current performance with NFET/PFET IDSAT = 825/950 μA/μm (circumference normanlized) or 2592/2985μA/μm (diameter normanlized) at supply voltage VDD = 1 V and off-current IOFF = 15-30 nA/μm. Superior NW uniformity is obtained through the use of a combined hydrogen annealing and oxidation process.

Relationship between mobility and high-k interface properties in advanced Si and SiGe nanowires
Tachi K., et al. (Leti)
For the first time, interface properties between high-k and Si or SiGe nanowires (NWs) have been experimentally investigated by adapting charge pumping techniques and low-frequency noise measurement.

One-Transistor Nonvolatile SRAM (ONSRAM) on Silicon Nanowire SONOS
Ryu S.-W., et al. (KAIST)
A one-transistor nonvolatile SRAM (ONSRAM) on a silicon nanowire (SiNW) SONOS is demonstrated. A nonvolatile memory (NVM) property is attained by employment of
O/N/O gate dielectric stacks as an electron storage node, and SRAM functionality is achieved by exploiting latch phenomena of a floating body in SiNW.

A stacked SONOS technology, up to 4 levels and 6nm crystalline nanowires, with gate-all-around or independent gates (Φ-Flash), suitable for full 3D integration
Hubert A., et al. (Leti)
The authors present the first experimental study of a Gate-All-Around (GAA) SONOS memory architecture with 4-level crystalline nanowire channels (down to 6nm-diameter). The technology is also extended to an independent double gate memory architecture, called Φ-Flash. The experimental results with 6nm nanowires show high programming windows (up to 7.4V), making the structure compatible with multilevel operation. Excellent retention even after 104 cycles is achieved.

16nm Functional 0.039mm2 6T-SRAM Cell with Nano Injection Lithography, Nanowire Channel, and Full TiN Gate
Hou-Yu Chen, et al. (NDL Taiwan, UC Berkeley)
Record area size of 0.039mm2 for a functional 6T-SRAM cell has been successfully achieved with a novel Nano Injection Lithography (NIL) technique and dynamic Vdd regulator (DVR).