Advanced Substrate Corners - ASN #14 - Professor's Perspective

The right choice for 22nm SRAM

Posted by and (UC Berkeley) on December 4, 2009
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What is the best transistor structure to meet SRAM performance and yield requirements at the 22nm node? The semiconductor device research group at UC Berkeley pioneered the FinFET structure in 1998. Now SOI-based FinFETs lead the field of candidate structures to eventually replace the planar bulk MOSFET. In the near term, yield and manufacturability may trump performance for high-volume markets, however.

Our work recently presented at the 2009 IEEE SOI Conference indicates that a planar fully depleted (FD) structure on very thin-BOX (~10nm thick) is a compelling candidate. Specifically, we found that for 6T-SRAM cells at the 22nm node:

  • planar FD-SOI structures on thin-BOX are significantly better than planar bulk-Si structures, in terms of both performance and yield;
  • although planar FD-SOI structures on thin-BOX cannot yet match FinFETs in performance, their performance is adequate and they are easier to manufacture for high-volume applications demanding high yields.

A summary of our recent findings follows.

Figure 1. As seen in this comparison, only the thin-BOX FD-SOI MOSFET technology is capable of attaining the requisite 6-sigma yield requirement for 6-T SRAM cells at the 22nm node.

Better than bulk

In our paper, “SRAM Yield Enhancement with Thin-BOX FD-SOI” [1], we compared the planar thin-BOX FD-SOI vs. planar bulk MOSFETs, in terms of 6-T SRAM cell performance and yield at the 22nm node.

We found the following advantages of thin-BOX FD-SOI technology:

  • Random threshold-voltage variation (sigma-Vth) is reduced by 50% due to the elimination of dopants in the channel region and improved suppression of short-channel effects.
  • Cell write-ability is improved by 30%, for the same read static noise margin (SNM).
  • Six-sigma cell yield can be achieved with a minimum power-supply voltage (VDD) of 0.6 Volts.  In contrast, it will be difficult for planar bulk-Si SRAM technology to meet the six-sigma yield requirement for any value of VDD up to 0.9 Volts.

The improved write current and higher cell sigma lead us to conclude that planar FD-SOI structures on thin-BOX are promising for continued 6-T SRAM cell area scaling.

Figure 2. These graphs compare estimated SRAM cell yield as a function of cell operating voltage. “Dual-fin” refers to a FinFET cell that utilizes dual-fin pull-down devices (for higher cell beta ratio, i.e. higher read stability), while “Single-fin” refers to a FinFET cell that utilizes single-fin pull-down devices. (a) yield of read static noise margin (RSNM), (b) yield of write-ability current (Iw). Only the planar FD-SOI MOSFET can comfortably attain the 6-sigma yield level.

Higher yielding than FinFETs

In our invited paper, “SRAM Cell Design Considerations for SOI Technology” [2], we compared SOI-based FinFETS with planar FD-SOI MOSFETS on thin BOX, in terms of 6-T SRAM cell performance and yield at the 22nm node.

FinFET technology can attain significantly superior performance, specifically higher read static noise margin (SNM) and write-ability current (IW). However, if the fin width is 2/3 times the gate length (LG), it will have higher sensitivity to random and process-induced variations, resulting in lower yield for a comparable cell area. Thus, in order to meet the six-sigma yield requirement at the 22nm node, the fin width must be much less than 2/3 times LG, which presents a significant challenge for manufacturing. Thin-BOX planar FD-SOI MOSFET technology, on the other hand, can meet the six-sigma yield requirements with a body thickness that is ~1/4 times LG. Recent advancements by Soitec to dramatically improve the thickness uniformity of SOI and BOX layers make this technology more manufacturable.

[1] “SRAM Yield Enhancement with Thin-BOX FD-SOI” Changhwan Shin, Min Hee Cho, Yasumasa Tsukamoto, Bich-Yen Nguyen, Borivoje Nikolic, Tsu-Jae King Liu. (UC Berkeley, Soitec, Renesas) International SOI Conference, October, 2009.
[2]
“SRAM Cell Design Considerations for SOI Technology” (invited). Tsu-Jae King Liu, Changhwan Shin, Min Hee Cho, Xin Sun, Borivoje Nikolic, Bich-Yen Nguyen (UC Berkeley, Soitec). International SOI Conference, October, 2009.