ASN #10 - News & Viewpoints - SOI In Action

3D ICs: Opportunities & Timing

Posted by (Yole Développement) on August 16, 2008
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A new study from Yole on 3D ICs sees a bright future for applications, markets and active layer transfer technology.

Chip performance, size and functionality – especially for consumer electronics – will drive the industry to adopt 3D stacked chips with through-silicon vias (TSVs) replacing wire bonding for certain markets in the 2009-2015 time frame.

The technical issues for innovative 3D packaging at the wafer level are close to being solved.
Stacking memories, stacking memories and logic, MEMS on CMOS and image sensors with microprocessors will be the first mass market applications.

Image sensors first

Here at Yole, we first predicted that image sensors would be the next “killer app” for TSV two years ago. Successive announcements from Toshiba, Oki, STMicroelectronics, Micron and Tessera-ShellCase have proved us right.

This is just a first step into a long and complex overall technology roadmap. We see the next applications in wireless system-in-package (RF-SiP) and memories (Flash and DRAMs).

Figure 1. 3D TSV wafer forecast Reference: Yole 3D IC & TSV Report ©2008 Yole Développement.

Memory nex

Memory is next in line. For DRAMs, the density and performance drivers are clear. Flash (NAND & NOR), on the other hand, is not designed for speed, so wire-bond interconnect technology could meet the requirements for 3D packaging. However, form factor and density limitations may push Flash to stacking with TSV within the next three years, with ten dies vertically stacked in a total package height thinner than 1.0mm.

Figure 1 shows our detailed forecast for 3D TSV wafers to be shipped in the 2008-2014 time frame. We forecast that about 200,000 yielded wafers (200mm-equivalent) will be processed with TSVs this year.

Wafer level transfer

The advent of 3D ICs will open the door to further innovation. For example, we see Tracit Technologies’ low-temperature direct oxide bonding as a powerful approach for wafer-level circuit transfer technology in applications including image sensors, photonic circuits and 3D-integration.

For CMOS image sensors, Tracit’s circuit layer transfer technology is currently delivering back-illumination capabilities. This technology dramatically improves sensor sensitivity compared to standard front-illuminated sensors.

By 2010-2011, when the market for the integration of heterogeneous components such as memories, power ICs and analog takes off, Tracit’s transfer technology will simplify device design and manufacturing with hybrid function capability and technology integration

From that point on, the market will really soar. In 2007, 0.5 million wafers were processed. By 2014, the number of processed wafers will be 16.6 million with a 56% CAGR over 2007/2014.