Tagged with apps, high-perf, high-temp, III-V, mil/aero, rf, Soitec
Advanced engineered substrates are a key to the Raytheon-led DARPA COSMOS project to integrate compound semiconductors and silicon CMOS on a single chip.
In what we believe to be an industry first, a Raytheon Company-led team has demonstrated the industry’s first Indium Phosphide (InP)-based heterojunction bipolar transistor (HBT) fabricated on a silicon wafer. HBTs are high-mobility, compound semiconductor (CS) transistors used primarily in RF and radar applications.
The team developed a process for directly growing a CS on a uniquely engineered silicon substrate. This innovation provides a technical approach that is creating a new class of high-performance circuits integrating CS and silicon-based CMOS on a single chip. It starts with a single wafer to enable more affordable military applications.
The accomplishment marks a key step and is a critical building block contributing to the ultimate success of DARPA’s Compound Semiconductor Materials on Silicon (COSMOS) program. This highly innovative technique has been developed under a $6.5 million contract awarded by the Office of Naval Research and funded by the Defense Advanced Research Projects Agency.
Combining the best attributes of CS and CMOS will enable CS performance with CMOS affordability. Our approach differs from others in that it requires a single wafer to achieve a finished chip. This eliminates costly device transfer, wafer bonding and assembly steps. As such, restrictions on the placement of the CS devices on the starting wafer are also eliminated, resulting in simple, high yield, monolithic integration.
Elegant Substrate Engineering
The starting material is a unique silicon template wafer called silicon-on-lattice engineered substrate (SOLES). SOLES wafers resemble a stack consisting of an SOI wafer on top of a germanium-on-insulator on silicon (GeOI/Si) wafer. The embedded germanium layer serves as a template for the growth of the CS stack.
The process flow on the SOLES template wafer is as follows:
1. front end CMOS device fabrication,
2. selective window opening for the HBT devices,
3. InP HBT epitaxial growth,
4. InP HBT device processing, and
5. interconnects between the InP HBT devices and CMOS.
Complex development simplified
The SOLES wafer also greatly simplifies development of the interim steps. Part of our team worked on the CMOS development on standard SOI wafers, while others worked on developing the CS stack on standard GeOI wafers.
To the best of our knowledge, in the CS work we have demonstrated for the first time the direct epitaxial growth of InP HBT structures on composite InAlAs/GaAs metamorphic buffer (M-buffer) layers on GeOI substrates. The HBTs demonstrate a peak current gain cutoff frequency Ft of 170 GHz at a nominal collector current density of 2mA/μm².
With these interim steps successfully achieved, we can move on to the final work on the SOLES wafer, wherein the CS and CMOS devices are created side-by-side in a very small area. This requires one additional step wherein we etch a window through the top silicon down to the embedded Ge template. The InP HBT is then created in that window.
Ultimately, the InP HBT and the CMOS device are interconnected, resulting in an elegant solution with optimal circuit performance.
Reference: “Direct Growth of Compound Semiconductors on Silicon”, Jeffrey LaRoche, Katherine J. Herrick and Thomas E. Kazior, Raytheon, Tewksbury, Massachusetts, USA; Amy W. K. Liu, IQE Inc., Bethlehem, Pennsylvania, USA; Miguel Urteaga and Berinder Brar, Teledyne Scientific Company, Thousand Oaks, California, USA; Mayank T. Bulsara and Eugene A. Fitzgerald, Department of Materials Science and Engineering, Massachusetts Institute of Technology, Cambridge, Massachusetts, USA; David Clark, Raytheon, Glenrothes, Scotland; Nicolas Daval and George K. Celler, Soitec, France.
Materials Research Society (MRS) Spring Meeting, 2008.