Tagged with design, FD-SOI, UC Berkeley
Might the Back-Gated FD-SOI MOSFET be the ultimate transistor structure?
The fully depleted silicon-on-insulator (FD-SOI) MOSFET structure has been proposed for scaling CMOS technology to sub-45nm nodes. This is because short-channel effects (manifested in increasing off-state leakage with increasing drain bias and with decreasing gate length) are well suppressed in a FD-SOI MOSFET when the body thickness (TSi) is less than or equal to one-fourth of the gate length (LG).
However, as LG is scaled below 20nm, TSi must be scaled below 5nm, so that large parasitic series resistance and threshold-voltage sensitivity to TSi variation due to quantum confinement effects become serious issues.
The double-gate MOSFET structure avoids these issues because the body thinness requirement is less stringent: TSi can be as large as two-thirds of LG. However, doublegate transistor structures such as the vertical FinFET are more challenging to manufacture than the planar FD-SOI MOSFET structure.
Very thin BOX
A solution to this dilemma is the back-gated FD-SOI MOSFET structure, which can be easily implemented using a SOI wafer substrate with a very thin buried oxide (BOX) layer (Figure 1).
The back gate electrode can be used for dynamic threshold voltage (VTH) control, to optimize the tradeoff between high performance (low VTH) and low power (high VTH), or to compensate process-induced VTH variations to improve parametric yield.
More interestingly, reverse back-gate biasing suppresses short-channel effects and thus can be used to relax the body thinness requirement of a FD-SOI MOSFET, to make it comparable to that for the double-gate MOSFET.
For optimal BG-MOSFET performance (smallest switching delay), the BOX thickness should be thicker than the gate-dielectric thickness to balance the tradeoff between parasitic source/drain capacitance and electrostatic integrity.
The BG-MOSFET structure can also be attractive for implementing a capacitor-less DRAM cell in which information is stored in the form of charge in the body region, at the back channel surface near to the source.
Since the electrically floating body region (where the charge is stored) is induced by back-gate biasing rather than by heavy body doping, this cell design avoids statistical dopant fluctuation effects and hence is more scalable than a single-gate PD-SOI cell design for future high-density memories.