Advanced Substrate Corners - ASN #9 - R&D/Labnews

SOI Substrates Meet Needs of Advanced Devices

Posted by (Soitec) on May 14, 2008
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The ITRS calls for ultra-thin body devices to enter manufacturing in just a few years. The stringent SOI substrate requirements are met with high-volume manufacturing technology.

SOI technology is developing toward Ultra-Thin Body (UTB) semiconductor layers with fully depleted (FD-SOI) and Multiple Gate FETs (MuGFETs), consistent with the latest version of the ITRS.

The current path of scaling bulk and bulklike partially depleted (PD) SOI, while meeting performance, density, and power requirements, becomes exceedingly difficult.

Specifically:

  • SRAM cells are more and more difficult to make due to the Vt local mismatch.
  • Short channel effects (SCE) become dominant.
  • Shallow trench isolation is not scaling properly in the transition from the current 45nm node to 32nm.
  • Uniaxial stressors are losing efficiency and options like removable spacer and biaxial strain provide little room around those difficulties.
  • Finally, the soft-error rate is excessive.

UTB solves challenges

UTB MOSFETs with undoped channels and body thickness (Tbody) of less than 10 nm minimize these problems because of their high immunity to short channel effects (SCE) and 2 to 3X reduction in the Vt mismatch (see Figure 1).

UTB also provides almost ideal sub-threshold slope (SS) that translates into better Ion/Ioff ratio, and equally important, gives a DIBL of less than 100mV/V, thus allowing faster transistor switching, better Vdd scaling and denser logic.

In addition to High Performance (HP) devices, UTB SOI technology also benefits Low Operating Power (LOP) devices, as they can exhibit a relatively wider design window. And in analog technology, UTB will provide better intrinsic gain behavior.

Substrate manufacturing

Soitec has developed high volume manufacturing technology for 300mm UTB SOI wafers with excellent thickness uniformity. Currently Tbody of 10nm +/- 1nm is possible, and progress is being made toward even tighter specs.

In addition to conventional ultra-thin SOI layers, biaxially strained layers and multicomponent films can also be available for mobility enhancement, while ultra thin BOX offers better SCE immunity and back gate bias capability.

ITRS : 2010

Many R&D organizations have demonstrated the superior performance and robustness of FD devices made in UTB-SOI.

As illustrated in other articles in this edition of ASN, SRAM stability has been dramatically improved, and parasitic resistance, which was excessive in early development phases of FD-SOI, has been significantly reduced by selective epi techniques.

According to the ITRS projections, FD-SOI is expected in manufacturing around 2010.

Figure 1. Threshold voltage mismatch, comparing undoped channel UTB in FD-SOI to Bulk and PD-SOI mismatch test structures.UTB FD-SOI improves mismatch by 2x compared to bulk and PDSOI CMOS. (Source: Freescale – Thean et al, 2003 IEDM)

MuGFETs use conventional SOI

MuGFETs on SOI are another version of UTB devices. Here, thin bodies are defined by lithography and etch stop on Buried Oxide, instead of using a high degree of process complexity to fabricate the thin bodies on a bulk substrate.

ITRS predictions are for commercial introduction of this technology about 2011, in parallel with planar FD devices, but more likely to last for many device generations. MuGFETs are fully compatible with conventional SOI substrates that are mass-produced for the current partially depleted applications.