Advanced Substrate Corners - ASN #8 - R&D/Labnews

SOI for Memory Applications

Posted by (Soitec) on October 31, 2007
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SOI-based memory reverses cache crunch and simplifies DRAM scaling, boosting performance and reducing cost.

2006 Revenues $60.3 billion Memory Market Percentage by Device (Source: Gartner Research, ICMTD May 2007)

Memory today represents about 25% of the estimated $260B worldwide semiconductor market. The two dominant players are DRAM (56%) and FLASH (33%). Further, memory in the form of embedded SRAM cache is becoming the dominant area user and technology driver for logic (20% of the market). Hence, memory is poised to control about half of the worldwide semiconductor market. SOI has a strong potential to become a key player in this area.

In today’s high performance or low power, 50-80% of chip area is SRAM cache. However, SRAM suffers from two main drawbacks: large area (e.g., 0.34μ² vs. 0.06μ² for DRAM for ~45nm nodes) and poor cell stability (‹45nm Lg due to Vt mismatch from high dopant, random dopant fluctuations in bulk).

1T-RAM concepts such as ZRAM or FBC, which utilize charge retention in an SOI transistor, can replace SRAM for higher-level cache (L2/L3), taking advantage of the 3-5x higher density, resulting in die size reduction. Further, stability of SRAM, which can not be replaced at the lower levels due to need for greater speed, can benefit from undoped fully depleted FD devices on SOI due to reduced random doping fluctuation (RDF) compared to bulk. Both SRAM constraints, density and stability will require SOI substrates.

DRAM savings

In DRAM, the demand for higher density requires capacitor scaling. For trench DRAM, aspect ratios exceeding 100 are expected ‹60nm, and the need for ever-higher K dielectric requires new material every generation.

In stacked capacitor DRAM, mechanical reliability of the capacitor is a major concern. Here also, a 1T-RAM solution eliminating the need for capacitors can greatly simplify the process leading to 30% cost reduction, plus a transistor based scaling path

Further, short channel effects have caused DRAM users to adopt 3D devices, which resemble inverted FinFETs built on bulk. Such devices have moderate performance and control. SOI would allow a more robust, higher performance device especially for peripheral circuits. Further improvement in retention through reduced leakage can be in the fully depleted (FD) mode.

Finally, FLASH scaling requires FinFET devices for higher drive currents and better SNM. FinFlash profits the most from the SOI substrate that offers electrical isolation, mechanical stability, and more robust fin patterning.