Tagged with 20/22nm, design, FD-SOI, FinFET, Freescale, R&D
One of the world’s leading experts, Professor Fossum explains why SOI represents a pragmatic approach to future transistor generations.
Based on our recent studies of multi-gate MOSFETs (“MuGFETs”) for CMOS applications, which are mainly modeling- and simulation-based with experimental support from Freescale Semiconductor, we have suggested that nanoscale FinFETs can and should be designed pragmatically, with:
• double gates (DG),
• a near-midgap metal (for both nMOS and pMOS),
• an undoped ultra-thin fin-body (UTB),
• a relatively thick nitrided oxide (no high-k dielectric needed),
• and an optimal gate-source/drain underlap.
UTBs can yield very high carrier mobilities. We have projected outstanding performance for DG FinFET CMOS scaled to the end of the official SIA roadmap, for SRAM as well as high-speed (and low-power) logic circuits.
Most of the DG-FinFET technology development is being done with SOI wafers, although there is some being done with conventional bulk-Si wafers to explore the trade-offs in process complexity.
Here is a perspective, shared by us and Freescale. The advantages of SOI clearly make it the preferred material:
1) As we have seen in novel approaches like the ITFET structure*, SOI renders fin stability comparable to bulk Si.
2) SOI provides device/circuit design flexibility.
3) Effective device isolation on SOI is much easier technologically.
4) Source/drain junction capacitance is virtually nonexistent with undoped UTBs on SOI.
5) For similar reasons, source/drain junction leakage current is negligible.
6) Most importantly, the underlying BOX effectively suppresses the source-drain leakage current under the gated fin-body (see the figure). Bulk Si would require heavy doping to suppress this current, as well as to effect reasonable device isolation. But one of our goals with MuGFETs is to get away from doping and the random effects it causes: the only pragmatic way to do that is to put the UTB FinFET on SOI.
|* L. Mathew, et al., Tech. Digest 2005 International Electron Devices Meeting, p. 731, Dec. 2005.|