Advanced Substrate Corners - ASN #4 - R&D/Labnews

Strained Silicon on Insulator: the Wafer Solution for Low-Power and High-Performance Devices

Posted by (Soitec) on April 6, 2006
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sSOI is on-track for high-volume manufacturing at the 45nm node.

The end of conventional scaling is a topic that has generated discussion and controversy within the semiconductor community. The fact is that IC density increase through device geometry shrinking no longer results in an IC performance increase if the scaling is not coupled to the introduction of new materials. The addition of new materials has always been present in the CMOS world, but it has become the dominant “scaling” approach beyond the 90nm technology node.

The most important innovation at the transistor level is the introduction of mobility engineering through Si substrate straining techniques. Process-induced stress has been known for many years. For example, silicidation, STI isolation, and cap layers all induce a certain level of device geometry dependent stress that can be beneficial or detrimental to transistor performance. The challenge is to optimize all CMOS process modules, i.e. their uniaxial stressor components, in order to maximize beneficial effects while minimizing the negative contributions. The IC industry has intensively developed the stressors techniques making it possible for uniaxial strained silicon to make its way into 90nm IC manufacturing.

At the substrate level a similar development has occurred. Strained silicon on insulator (sSOI) has been developed by Soitec as the solution that offers higher carrier mobility, combining the advantages of SOI with those of strained silicon. The fundamental difference between the uniaxial and the wafer level (biaxial) strained Si is that the former is introduced during CMOS processing while the latter is built into the substrate. As a consequence, sSOI wafers offer tensile strain that is device-layout and gate-pitch independent, giving IC design a high degree of freedom. The sSOI evaluation by IC manufacturers highlights its potential as a low power, high performance solution. On-going work with IC makers and research institutes shows that the combination of uniaxial stressors and sSOI amplifies the mobility enhancement of both n- and p-channel devices.

Anticipating the IC industry 45nm node requirements, Soitec has accelerated its sSOI development by ramping up its 300mm capacity to pilot line levels, preparing for the manufacturing phase. The payback can already be seen. sSOI quality is improving rapidly and moving towards SOI wafer quality standards. sSOI wafer availability has met the market expectations in a timely manner and it has led to evaluation of this technology at several leading edge IC makers worldwide.

sSOI is the necessary next step for boosting transistor performance and for overcoming the future geometry limitations imposed by techniques that scale uniaxial stressors. sSOI also provides a solution for minimizing the IC power consumption by reducing the supply voltage and leakage currents without a circuit performance penalty.