Tagged with R&D, strain
The list of partners in the Medea+ Strained Silicon-On-Insulator Substrates for High Performance ICs program, known as SilOnIS, has now been made public. Among the corporate partners are AMD, ASM, Freescale, Infineon, Philips, Siltronic and ST, among others. Lead by Soitec, the project’s stated goal is to “…combine high-mobility, wafer-level strained silicon and SOI in a single technology platform for high performance chips.”
For more information, see www.medeaplus.org/web/downloads/profiles/2T101_profile.pdf.