Tagged with markets, Semico, SOI
A new Semico Research study estimates the impact of SOI on the bottom line.
As semiconductor process technologies move down the nanometer scale from 90nm to 65nm and smaller, the benefits of silicon-oninsulator (SOI) wafers in reducing junction capacitance, improving the short-channel effect, reducing leakage and decreasing soft error rates become more and more attractive. Although these variables provide a number of advantages for chips requiring high performance at low power, the widespread adoption of SOI wafers still faces both real and perceived challenges.
New opportunities for SOI are increasing with design innovations that leverage silicon savings. Optimized SOI design solutions developed by SOISIC for digital logic and Innovative Silicon for embedded memories are offering die size reduction up to 40% depending on product specification.
Recently, Semico Research completed a study analyzing semiconductor wafer processing costs to compare the impact of bulk silicon versus SOI substrate costs on the production of semiconductors today and on potential products using optimized SOI design solutions.
Semico Research utilized several methods to analyze the cost or value of SOI in the manufacture of semiconductor products.
Analyzing the cost/benefit of SOI wafers is challenging due to the number of scenarios in which SOI can be used to improve die shrink or performance or a combination of both. Semico applied different variables including device and process complexity and node transition, to depict the cost impact of SOI from a very high level, down to a more detailed product level.
On a straight manufacturing cost basis, the 10-15% cost-of-ownership (COO) figure commonly referred to in the industry is incomplete: it doesn’t tell the whole story. It is a scenario that only considers the impact of wafer cost on wafer manufacturing, using a very aggressive foundry cost model as a reference.
Moving further into the semiconductor manufacturing process, if you consider the cost of SOI once the wafer is tested, diced and the good die packaged, the Semico analysis has found that SOI COO adds only 4 to 6% to the total manufacturing cost. If at any point, you do basic design optimization of the digital logic, SOI COO is cut by another 10%. In this case, SOI is cheaper than bulk at 90nm for the large die sizes. And starting at 65nm, with basic design optimization of the digital logic, SOI is almost always cheaper than bulk.
Furthermore, if you look from the vantage point of the average selling price (ASP) of an SOI-based chip, even without any design optimization the situation is favorable. The cost of the decision to start with an SOI wafer has a very minor impact: SOI COO represents less than 1% of the ASP.
New design solutions will drive SOI to an even more favorable cost position. Use of memory optimization tools can increase the benefits of SOI from breakeven to a cost reduction of over 40%, depending on the product, technology and process complexity (1). Considered in this broader context, SOI can become a cost-effective and attractive solution.
(1) Source: Semico Research Corp. Cost of Ownership White Paper: SOI. March 2006.