Tagged with design, R&D, SOI, Soitec, strain, wafers
IC makers need both local and global strained SOI to win the GHz race.
At the device level, the switching speed of MOS logic transistors (gate delay) is limited by two factors:
1. The times required to charge and discharge the parasitic capacitances that exist between electrodes and the body substrate.
2. The transit time of charge carriers through the channel, which is dependant on transconductance gm = µ Cox (W/L), where µ is the carrier mobility (µe, µh) and Cox is the gate oxide capacitance.
SOI resolves the capacitance issue by providing a partially depleted (thin SOI) or fully depleted (ultra-thin SOI) layer of silicon isolated from the substrate. Moreover, the SOI transistor isolation allows optimized integration density and chip size. Thus SOI is the substrate of choice for leading MPU IDMs in the GHz race. For the current and upcoming generation, the addition of local strain addresses NMOS & PMOS channel mobility enhancements separately.
Strained SOI (sSOI) is a new engineered substrate, which can be either partially or fully depleted. Its uniformly stretched Si channel can provide an increase of up to 2x in electron mobility (µ e ) on the whole wafer surface, with an immediate impact on NMOS. As it is compatible with additional local strain features, the optimal solution in the GHz race is sSOI plus local strain for PMOS. The winners will be using both. •