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More Good FD-SOI News from DATE Conference – ST, Leti, Mentor, CMP Thumbnail

More Good FD-SOI News from DATE Conference – ST, Leti, Mentor, CMP

Posted by on May 22, 2013
In Editor's Blog
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At the recent DATE Conference in Grenoble (DATE is like DAC, but in Europe, alternating yearly between Grenoble and Dresden), STMicroelectronics, CEA-Leti & Mentor Graphics joined forces for a FD-SOI presentation organized by CMP and sponsored by Mentor. Here are some of the highlights (the complete presentations are all available from the CMP website). FD-SOI: …

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IEEE SOI Conference (Oct., Monterey) Expands, Extends Call for Papers Thumbnail

IEEE SOI Conference (Oct., Monterey) Expands, Extends Call for Papers

Posted by on May 17, 2013
In Advanced Substrate Corners, Conferences
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IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference Hyatt Regency Monterey Hotel and Spa, Monterey, California October 7th thru 10th, 2013 In 2013, an exciting new event named IEEE S3S will take place in Monterey, CA. This industry-wide event is founded upon the co-location of two IEEE conferences that have been at the leading edge of CMOS …

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ST’s FD-SOI Wins EETimes ACE Award… and Customers! Thumbnail

ST’s FD-SOI Wins EETimes ACE Award… and Customers!

Posted by on May 2, 2013
In Editor's Blog
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Two important FD-SOI wins for STMicroelectronics have just been announced: The EETimes ACE Award for Energy Technology; Customers. The Energy Technology Award was presented at a ceremony for the 2013 Annual Creativity in Electronics (ACE) Awards. It is given by EETimes and EDN, two of the most prominent trade-media sources in electronics. The ACE Awards …

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IBM: FinFET Isolation Considerations and Ramifications – Bulk vs. SOI Thumbnail

IBM: FinFET Isolation Considerations and Ramifications – Bulk vs. SOI

Posted by (IBM) on April 18, 2013
In Advanced Substrate Corners, Design & Manufacturing, In & Around Our Industry, R&D/Labnews
Tagged with , , , , , , , , , ,

Fully-depleted transistor technologies, both planar and fin-type, are now in the mainstream for product designs. One of the many interesting topics in the new 3D FinFET technology is the approach to isolation. In this article, key elements that differentiate junction-isolated (bulk) and dielectric-isolated (SOI) FinFET transistors are discussed, encompassing aspects of process integration, device design, …

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GF’s Two Flavors of FD-SOI – Kengeri Explains (Exclusive ASN Q&A) Thumbnail

GF’s Two Flavors of FD-SOI – Kengeri Explains (Exclusive ASN Q&A)

Posted on April 15, 2013
In Design & Manufacturing, In & Around Our Industry
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Hearing the news that GlobalFoundries would be offering two flavors of FD-SOI, ASN asked the company to explain the strategy further. Here are the responses provided by Subi Kengeri, Vice President of Advanced Technology Architecture. What do you see as the FD-SOI benefits for chip designers? Lower SRAM Vmin for retention and lower operating Vmin …

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