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Consortium Website – What’s New Thumbnail

Consortium Website – What’s New

Posted on May 2, 2012
In ASN #19, Special supplement: SOI Industry Consortium

Presentations At the SOI Consortium’s 6th FD-SOI workshop (held just after ISSCC), excellent talks were given by STMicroelectronics, IBM, ARM, Leti, Soitec, Accelicon and UC Berkeley. Most of the presentations are freely available for downloading from the SOI Consortium website. As Horacio Mendez, Executive Director of the SOI Consortium concluded, this workshop was great. “We’ve …

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FD-SOI – A Look at Consortium Benchmarking Results Thumbnail

FD-SOI – A Look at Consortium Benchmarking Results

Posted on May 2, 2012
In ASN #19, Special supplement: SOI Industry Consortium

STMicroelectronics, IBM, ARM, GLOBALFOUNDRIES, Soitec and other leading semiconductor companies in the SOI Consortium recently participated in a benchmarking study. Each tackling different aspects, they detailed the interest of planar FD-SOI as early as the 28nm and 20nm technology nodes, in terms of performance, power and manufacturability. The joint research was performed by using an …

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Leti: Adding Strain to FD-SOI for 20nm and Beyond Thumbnail

Leti: Adding Strain to FD-SOI for 20nm and Beyond

Posted by Olivier FAYNOT and Francois ANDRIEU (CEA-Leti) on April 30, 2012
In Advanced Substrate Corners, ASN #19, R&D/Labnews
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Work at Leti shows that strain is an effective booster for high-performance at future nodes. The outstanding electrostatic performance already reported for planar FD-SOI technology can be improved by the use of ION boosters in order to target-high performance applications, as already demonstrated in the past. As illustrated in Figure 1, strain can be incorporated …

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ST White Paper Excerpts: Planar Fully-Depleted Silicon Technology to Design Competitive SOCs at 28nm and Beyond Thumbnail

ST White Paper Excerpts: Planar Fully-Depleted Silicon Technology to Design Competitive SOCs at 28nm and Beyond

Posted by Philippe FLATRESSE, Giorgio CESANA, and Xavier CAUCHY (Soitec) on April 24, 2012
In ASN #19, Design & Manufacturing, In & Around Our Industry
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STMicroelectronics recently issued a major white paper detailing the choice of FD-SOI for consumer SOCs at 28nm and beyond. This article excerpts some of the highlights. From “Planar Fully-Depleted Silicon Technology to Design Competitive SOC at 28nm and Beyond” (White paper by STMicroelectronics and Soitec): “ FD-SOI Executive Summary Planar FD is a promising technology …

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Chenming Hu: SOI Can Empower New Transistors to 10nm and beyond Thumbnail

Chenming Hu: SOI Can Empower New Transistors to 10nm and beyond

Posted by Chenming HU (UC Berkeley) on April 23, 2012
In Advanced Substrate Corners, ASN #19, Professor's Perspective
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FinFET and FD-SOI transistors look different but share a common principal that allows MOSFETs to be scalable to 10nm gate length. The good, old MOSFET is nearing its limits. Scaling issues and dopant-induced variations are leading to high leakage (Ioff) and supply voltage (Vdd),  resulting in excessive  power consumption and design costs. While these challenges …

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